Data transfer networks include network elements such as, for example, routers, switches, and terminal devices which communicate with each other via data transfer links between the network elements. In many data transfer networks, there is a need to achieve synchronization between clock signals prevailing at various network elements of a data transfer network. The network elements can be configured to constitute master-slave pairs in order to distribute timing information within a data transfer network. Each slave network element controls its clock signal generator so that a reference clock signal prevailing at the corresponding master network element is regenerated in the slave network element on the basis of timing messages transferred from the master network element to the slave network element. The timing messages can be time-stamps contained by protocol data units “PDU” that can be, for example, data packets or data frames. Each time-stamp indicates the instantaneous time value at the transmission moment of the respective protocol data unit containing the time-stamp under consideration, where the time value is based on the reference clock signal available at the master network element. It is also possible that the timing messages are timing packets that are transmitted so that the time interval between transmission moments of two successive timing packets is constant, or otherwise known, when being measured with the reference clock signal available at the master network element. It is also possible that one or more time-stamps indicating the transmission moments of one or more timing messages are transferred in one or more data packets transmitted after the one or more timing messages.
In many cases, the synchronization between network elements is accomplished as phase synchronization in which phase-error indicators are formed on the basis of reception moments of timing messages transmitted in accordance with the reference clock signal, and a phase-controlled clock signal is controlled in accordance with the phase-error indicators so as to achieve phase-locking between the reference clock signal and the phase-controlled clock signal. The phase-controlled clock signal is, however, susceptible to disturbances caused by the transfer delay variation of the timing messages. Thus, the weakness of this approach is that it tends to over-react to certain transfer delay variation characteristics. For example, 24 hours network loading patterns and/or large changes in the delay variation may cause problems in certain technologies such as, for example, asymmetric digital subscriber loops “ADSL”, microwave radios, and Gigabit passive optical networks “GPON”.
In conjunction with certain applications, e.g. the mobile 3rd generation “mobile 3G” and the succeeding Long Term Evolution “LTE” technologies, there is no phase error accumulation limit, thus phase synchronization is not an absolute requirement but the frequency synchronization is sufficient. On the other hand, modern oven controlled crystal oscillators “OCXO” are capable of producing a stable clock signal and also the cost/performance ratio of OCXOs is continuously improving. Therefore, instead of using the phase synchronization that is susceptible to disturbances caused by the transfer delay variation, a better result can be achieved by using a high-quality OCXO and frequency synchronization with a sufficiently long update interval that the adverse effect of the transfer delay variation can be reduced. However, this kind of synchronization arrangement is quite slow or even unable to respond to, for example, changes in the temperature of the OCXO and/or other changes in local circumstances.